1. Technical Field
The present disclosure relates to a frequency detecting circuit and, more particularly, to a frequency detecting circuit that operates using a digital control method, and a semiconductor apparatus including the same.
2. Discussion of the Related Art
To ensure circuit stability, integrated circuit cards such as smart cards need to operate only in a predetermined frequency range and to be entirely reset in a frequency range in which an error may occur in an internal circuit. For this operation, some semiconductor apparatuses, such as smart cards, include a frequency detecting circuit. The frequency detecting circuit detects a frequency of a clock signal input to a semiconductor apparatus and determines whether the frequency is in a normal range.
FIG. 1 is a schematic block diagram of a conventional frequency detecting circuit. The conventional frequency detecting circuit includes a pulse shaping circuit 110, a first filter 120, a second filter 130, and a detection signal generator 140.
The pulse shaping circuit 110 changes or divides the waveform of an input clock signal XCLK. The first and second filters 120 and 130 are low-pass filters (LPFs) and have a first cutoff frequency and a second cutoff frequency, respectively, where the first cutoff frequency is greater than the second cutoff frequency. Conventionally, the first and second filters 120 and 130 are implemented using an analog resistor-capacitor (RC) filter.
Table 1 below shows an ideal operation of the frequency detecting circuit illustrated in FIG. 1. Here, it is assumed that the first and second cutoff frequencies are 7.5 MHz and 500 kHz, respectively.
TABLE 1Operating frequencyHIGH_OUTHIGH_LOWFREQ_DETLower than second cutoffClock signalClock signalLOWfrequency (0~500 kHz)Between first and secondClock signal0HIGHcutoff frequencies(500 kHz~7.5 MHz)Higher than first cutoff00LOWfrequency (7.5 MHz~)
Referring to Table 1, when an input frequency is abnormally low, that is, when the input frequency is lower than the second cutoff frequency (0˜500 kHz), output signals HIGH_OUT and HIGH_LOW of the first and second filters 120 and 130 are clock signals toggling between a high level and a low level. When the input frequency is in a normal range, that is, when the input frequency is in a range between the first and second cutoff frequencies (500 kHz˜7.5 MHz), the output signal HIGH_OUT of the first filter 120 is a clock signal and the output signal HIGH_LOW of the second filter 130 is close to “0”. When the input frequency is abnormally high, that is, when the input frequency is higher than the first cutoff frequency (7.5 MHz˜), the output signals HIGH_OUT and HIGH_LOW of the first and second filters 120 and 130 are both close to “0”.
The detection signal generator 140 generates a detection signal FREQ_DET at the high level only when the output signal HIGH_OUT of the first filter 120 is the clock signal and the output signal HIGH_LOW of the second filter 130 is “0”, thereby indicating that the input frequency is in the normal range.
When an analog method using an analog RC filter is used for frequency detection, a large chip area is needed and a large amount of power is consumed. In addition, when the clock signal XCLK does not have a duty cycle of 50%, that is, when a high level period is short and a low level period is long or when a low level period is short and a high level period is long, the frequency cannot be detected using the analog method. As a result, a semiconductor device such as memory, which needs to operate normally in both of the high level period and the low level period of the clock signal XCLK, may operate erroneously.
Particularly, in an application such as a smart card in which a data value in the memory is very important, a high reliability of the frequency detecting circuit is required. Accordingly, a frequency detecting circuit for accurately detecting a frequency even when a clock signal whose duty cycle is not 50% is input and for limiting power consumption and decreasing a chip area is desired.